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18.2.1.1 Minimizing Cache Misses

Most CPUs have first-level instruction and data caches on chip and many have second-level caches that are bigger but somewhat slower. Memory accesses are much faster if the data is already loaded into the first-level cache. When your program accesses data that is not in one of the caches, a cache miss occurs. This causes a block of consecutively addressed words, including the data that your program just accessed, to be loaded into the cache. Since cache misses are costly, you should try to minimize them, using these tips:

Some framebuffers have cache-like behaviors as well. It is a good idea to group geometry so that the drawing is done to one part of the screen at a time. Using triangle strips and polylines tends to do this while simultaneously offering other performance advantages as well.


next up previous contents
Next: 18.2.2 Store Data in Up: 18.2.1 Optimize Cache and Previous: 18.2.1 Optimize Cache and
David Blythe
1999-08-06